Data Reduction and Parallelization for Human Detection System

HOG (Histogram of Oriented Gradients) is one of the effective ways for extracting feature values. Also, Real Adaboost algorithm has high recognition ratio, and it is adequate to hardware implementation. Many researches on human detection systems adopted these two algorithms and had achieved progress. However, data volume of HOG feature is still a problem in the whole system. Data volume from only one frame could be over 1 GB, and this data volume causes some difficulties from the view point of both sending data to a server and execution speed. Especially, many internal data communication between modules are required in hardware execution, much data volume could be a bottle-neck of the whole system operating speed. Here, a high speed and small memory consuming implementation of human detection system using Hardware-Software Co-design is proposed. For the executing speed of the system, HOG feature values are accelerated by an FPGA, and Real Adaboost detection is executed only by accessing ROM data in the FPGA. As a result, HOG+Real Adaboost part was accelerated about 23.1 times faster compared to the software execution. Whole system had been implemented on a single board, and it achieved 3.22 times speed up from camera input to VGA display output. Also we tried to reduce feature data volume, and achieved 93.75% of data compression compared to double precision calculation, with only 2.68% loss of the recognition accuracy.